74HC2G00-Q100; 74HCT2G00-Q100
Dual 2-input NAND gate
The 74HC2G00-Q100; 74HCT2G00-Q100 is a dual 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
Input levels:
For 74HC2G00-Q100: CMOS level
For 74HCT2G00-Q100: TTL level
Symmetrical output impedance
High noise immunity
Balanced propagation delays
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC2G00DC-Q100 | 2.0?-?6.0 | CMOS | ± 5.2 | 9 | 36 | 2 | low | -40~125 | 204 | 35.1 | 115 | VSSOP8 |
| 74HC2G00DP-Q100 | 2.0?-?6.0 | CMOS | ± 5.2 | 9 | 36 | 2 | low | -40~125 | 216 | 20.5 | 106 | TSSOP8 |
| 74HCT2G00DC-Q100 | 4.5?-?5.5 | TTL | ± 4 | 12 | 36 | 2 | low | -40~125 | 204 | 35.1 | 115 | VSSOP8 |
| 74HCT2G00DP-Q100 | 4.5?-?5.5 | TTL | ± 4 | 12 | 36 | 2 | low | -40~125 | 216 | 20.5 | 106 | TSSOP8 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC2G00DC-Q100 | 74HC2G00DC-Q100H (935300819125) |
Active | H00 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74HC2G00DP-Q100 | 74HC2G00DP-Q100H (935300821125) |
Active | H00 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 | |
| 74HCT2G00DC-Q100 | 74HCT2G00DC-Q100H (935300822125) |
Active | T00 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74HCT2G00DP-Q100 | 74HCT2G00DP-Q100H (935300823125) |
Active | T00 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
環境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HC2G00DC-Q100 | 74HC2G00DC-Q100H | 74HC2G00DC-Q100 |
|
|
| 74HC2G00DP-Q100 | 74HC2G00DP-Q100H | 74HC2G00DP-Q100 |
|
|
| 74HCT2G00DC-Q100 | 74HCT2G00DC-Q100H | 74HCT2G00DC-Q100 |
|
|
| 74HCT2G00DP-Q100 | 74HCT2G00DP-Q100H | 74HCT2G00DP-Q100 |
|
|
文檔 (12)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74HC_HCT2G00_Q100 | Dual 2-input NAND gate | Data sheet | 2024-08-13 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| mna099 | Block diagram: 74AHC2G00DC, 74AHC2G00DP, 74AHC2G00GD, 74AHCT2G00DC, 74AHCT2G00DP, 74AHCT2G00GD, 74AUP1G00GM, 74AUP1G00GW, 74AUP2G00DC, 74AUP2G00GD, 74AUP2G00GM, 74AUP2G00GT, 74HC2G00DC, 74HC2G00DP, 74HC2G00GD, 74HCT2G00DC, 74HCT2G00DP, 74HCT2G00GD | Block diagram | 2009-11-04 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
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