The 74HC/1 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT85 are 4-bit magnitude comparators that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (Q_A>B, Q_A=B and Q_A<B). The 4-bit inputs are weighted (A₀ to A₃ and B₀ to B₃), where A₃ and B₃ are the most significant bits.

The operation of the '85' is described in the function table, showing all possible logic conditions. The upper part of the table describes the normal operation under all conditions that will occur in a single device or in a series expansion scheme. In the upper part of the table the three outputs are mutually exclusive. In the lower part of the table, the outputs reflect the feed forward conditions that exist in the parallel expansion scheme.

For proper compare operation the expander inputs (I_A>B, I_A=B and I_A<B) to the least significant position must be connected as follows: I_A<B=I_A>B= = LOW and I_A=B= HIGH.

For words greater than 4-bits, units can be cascaded by connecting outputs Q_A<B, Q_A>B and Q_A=B to the corresponding inputs of the significant comparator.