74ALVCH16841
20-bit bus interface D-type latch; 3-state
The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
Features and benefits
Wide supply voltage range of 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Current drive ±24 mA at VCC = 3.0 V
MULTIBYTE? flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimize noise and ground bounce
All data inputs have bushold
Output drive capability 50 Ω transmission lines at 85 °C
3-state non-inverting outputs for bus oriented applications
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16841DGG | 1.2?-?3.6 | LVTTL | ± 24 | 2.4 | low | -40~85 | 93 | 21 | TSSOP56 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74ALVCH16841DGG | 74ALVCH16841DGG,11 (935259090118) |
Active | ALVCH16841 |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT364-1_118 |
文檔 (8)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74ALVCH16841 | 20-bit bus interface D-type latch; 3-state | Data sheet | 2024-07-10 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| sh00151 | Block diagram: 74ALVCH16841DGG | Block diagram | 2009-11-04 |
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| alvch16841 | alvch16841 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT364-1 | plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body | Package information | 2022-06-23 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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模型
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| alvch16841 | alvch16841 IBIS model | IBIS model | 2013-04-08 |
Ordering, pricing & availability
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