74LV07AT
Hex buffer with open-drain outputs
The 74LV07AT is a hex buffer with open-drain outputs. The outputs are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired?-?AND functions.
Designed to operate over a VCC range from 4.5 V to 5.5 V, the inputs are TTL compatible, which allows the device to be used to translate from 3.3 V to 5 V.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Features and benefits
Direct interface with TTL levels
Supply voltage range from 4.5 V to 5.5 V
Typical tPZL of 3.5 ns at 5 V
Typical VOL(p) < 0.8 V at VCC = 5 V, Tamb = 25 °C
Supports mixed-mode voltage operation on all ports
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA per JESD 78 Class II
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 3000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV07ATPW | 4.5?-?5.5 | TTL | ± 12 | 60 | 6 | low | -40~125 | 143 | 7.9 | 69 | TSSOP14 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LV07ATPW | 74LV07ATPWJ (935308209118) |
Active | LV07AT |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
文檔 (9)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LV07AT | Hex buffer with open-drain outputs | Data sheet | 2024-04-08 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| lv07at | lv07at IBIS model | IBIS model | 2017-06-02 |
| Nexperia_document_leaflet_Logic_LV-AT_201903 | LV-A(T) logic family | Leaflet | 2019-03-19 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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