可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經銷商處購買 |
|---|---|---|---|---|
| 74LVC374APW-Q100 | 74LVC374APW-Q100J | 935299317118 | SOT360-1 | 訂單產品 |
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Click here for more information74LVC374APW-Q100
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
The 74LVC374A-Q100 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.2 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC374APW-Q100 | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 2.7 | 100 | low | -40~125 | 101 | 4.6 | 45 | TSSOP20 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC374APW-Q100 | 74LVC374APW-Q100J (935299317118) |
Active | LVC374A |
TSSOP20 (SOT360-1) |
SOT360-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT360-1_118 |
Series
文檔 (13)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC374A_Q100 | Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive?-?edge trigger; 3-state | Data sheet | 2023-09-01 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
| lvc374a | lvc374a IBIS model | IBIS model | 2013-04-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP20_SOT360-1_mk | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT360-1 | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.2 mm body | Package information | 2024-11-15 |
| SOT360-1_118 | TSSOP20; Reel pack for SMD, 13''; Q1/T1 product orientation | Packing information | 2023-08-30 |
| 74LVC374APW-Q100_Nexperia_Product_Reliability | 74LVC374APW-Q100 Nexperia Product Reliability | Quality document | 2025-03-20 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態 | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVC374APW-Q100 | 74LVC374APW-Q100J | 935299317118 | Active | SOT360-1_118 | 2,500 |
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樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.