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Click here for more information74HC73DB
Dual JK flip-flop with reset; negative-edge trigger
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Alternatives
Features and benefits
CMOS low-power dissipation
- Wide supply voltage range from 2.0 to 6.0 V
- High noise immunity
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +80 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號(hào) | Package name |
|---|---|
| 74HC73DB | SSOP14 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC73DB | 74HC73DB,112 (935190270112) |
Obsolete | HC73 |
SSOP14 (SOT337-1) |
SOT337-1 |
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE |
暫無(wú)信息 |
| 74HC73DB,118 (935190270118) |
Obsolete | HC73 | SOT337-1_118 |
環(huán)境信息
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HC73DB | 74HC73DB,112 | 74HC73DB |
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| 74HC73DB | 74HC73DB,118 | 74HC73DB |
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文檔 (9)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74HC73 | Dual JK flip-flop with reset; negative-edge trigger | Data sheet | 2024-03-26 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SSOP14_SOT337-1_mk | plastic, shrink small outline package; 14 leads; 0.65 mm pitch; 6.2 mm x 5.3 mm x 2 mm body | Marcom graphics | 2017-01-28 |
| SOT337-1 | plastic, shrink small outline package; 14 leads; 0.65 mm pitch; 6.2 mm x 5.3 mm x 2 mm body | Package information | 2020-04-21 |
| SSOP-TSSOP-VSO-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
模型
No documents available
PCB Symbol, Footprint and 3D Model
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.