74LVC2G66-Q100
Bilateral switch
The 74LVC2G66-Q100 is a dual single pole, single-throw analog switch. Each switch has two input?/?output terminals (nY and nZ) and a digital enable input (nE). When nE is LOW, the analog switch is turned off. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 Ω (typical) at VCC = 2.7 V
6.5 Ω (typical) at VCC = 3.3 V
6 Ω (typical) at VCC = 5 V
Switch current capability of 32 mA
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD78 Class I
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數類型
| 型號 | Configuration | VCC (V) | RON (Ω) | Logic switching levels | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G66DC-Q100 | SPST-NO | 1.65?-?5.5 | 15 | CMOS/LVTTL | very low | -40~125 | 192 | 26.5 | 101 | VSSOP8 |
| 74LVC2G66DP-Q100 | SPST-NO | 2.3?-?5.5 | 15 | CMOS/LVTTL | very low | -40~125 | 196 | 15.1 | 99 | TSSOP8 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G66DC-Q100 | 74LVC2G66DC-Q100H (935301411125) |
Active | V66 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74LVC2G66DP-Q100 | 74LVC2G66DP-Q100H (935301412125) |
Active | V66 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
環境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G66DC-Q100 | 74LVC2G66DC-Q100H | 74LVC2G66DC-Q100 |
|
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| 74LVC2G66DP-Q100 | 74LVC2G66DP-Q100H | 74LVC2G66DP-Q100 |
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文檔 (12)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G66_Q100 | Bilateral switch | Data sheet | 2023-08-23 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| lvc2g66 | 74LVC2G66 IBIS model | IBIS model | 2015-02-19 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
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