74LVC4T3144-Q100
4-bit dual supply buffer/line driver; 3-state
The 74LVC4T3144?-?Q100 is a 4?-?bit, dual?-?supply level translating buffer with 3?-?state outputs. It features four data inputs (An and B4), four data outputs (YBn and YA4), and an output enable input (OE). The device is configured to translate three inputs from VCC(A) to VCC(B) and one input from VCC(B) to VCC(A). OE, An and YA4 are referenced to VCC(A) and YBn and B4 are referenced to VCC(B). A HIGH on OE causes the outputs to assume a high?-?impedance OFF?-?state.
The device is fully specified for partial power?-?down applications using IOFF. The IOFF circuitry disables outputs, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all outputs are in the high?-?impedance OFF?-?state.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Maximum data rates:
200 Mbps (3.3 V to 5.0 V translation)
140 Mbps (translate to 3.3 V))
100 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78B Class II
±24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 30 μA maximum ICC
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
JESD8-11A (1.4 V to 1.6 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (3.0 V to 3.6 V)
JESD12-6 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC4T3144PW-Q100 | n.a. | CMOS/LVTTL | ± 8 | 1 | low | -40~125 | 132 | 4.7 | 57 | TSSOP14 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC4T3144PW-Q100 | 74LVC4T3144PW-Q10J (935690173118) |
Active | C4T3144 |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
環境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC4T3144PW-Q100 | 74LVC4T3144PW-Q10J | 74LVC4T3144PW-Q100 |
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文檔 (8)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC4T3144_Q100 | 4-bit dual supply buffer/line driver; 3-state | Data sheet | 2024-02-22 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| lvc4t3144 | 74LVC4T3144 IBIS model | IBIS model | 2017-08-16 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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