74AVC16374
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374 consist of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE) are provided per 8-bit section.
The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance output state during power-up or power-down, nOE should be tied to VCC through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
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Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-1A (2.7 V to 3.6 V)
CMOS low power consumption
Input/output tolerant up to 3.6 V
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation
Low inductance multiple VCC and GND pins to minimize noise and ground bounce
Supports Live Insertion
Applications
參數(shù)類型
| 型號 |
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封裝
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AVC16374DGG | 74AVC16374DGG,112 (935265484112) |
Obsolete | AVC16374 Standard Procedure Standard Procedure |
TSSOP48 (SOT362-1) |
SOT362-1 |
SSOP-TSSOP-VSO-WAVE
|
暫無信息 |
| 74AVC16374DGG,512 (935265484512) |
Obsolete | AVC16374 Standard Procedure Standard Procedure | 暫無信息 | ||||
| 74AVC16374DGG,118 (935265484118) |
Obsolete | AVC16374 Standard Procedure Standard Procedure | SOT362-1_118 | ||||
| 74AVC16374DGG,518 (935265484518) |
Obsolete | AVC16374 Standard Procedure Standard Procedure | 暫無信息 | ||||
| 74AVC16374DGG,511 (935265484511) |
Obsolete | AVC16374 Standard Procedure Standard Procedure | 暫無信息 |
環(huán)境信息
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AVC16374DGG | 74AVC16374DGG,112 | 74AVC16374DGG |
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| 74AVC16374DGG | 74AVC16374DGG,512 | 74AVC16374DGG |
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| 74AVC16374DGG | 74AVC16374DGG,118 | 74AVC16374DGG |
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| 74AVC16374DGG | 74AVC16374DGG,518 | 74AVC16374DGG |
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| 74AVC16374DGG | 74AVC16374DGG,511 | 74AVC16374DGG |
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文檔 (10)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AVC16374 | 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state | Data sheet | 2017-05-03 |
| AN90007 | Pin FMEA for AVC family | Application note | 2018-11-30 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| mna578 | Block diagram: 74AVC16374DGG | Block diagram | 2009-11-04 |
| SOT362-1 | 3D model for products with SOT362-1 package | Design support | 2020-01-22 |
| avc16374 | 74AVC16374 IBIS model | IBIS model | 2019-01-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP48_SOT362-1_mk | plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body | Marcom graphics | 2017-01-28 |
| SOT362-1 | plastic thin shrink small outline package; 48 leads; body width 6.1 mm | Package information | 2024-01-05 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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