74AUP1G08-Q100
Low-power 2-input AND gate
The 74AUP1G08-Q100 is a single 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
CMOS low power dissipation
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
Low static power consumption; ICC = 0.9 μA (maximum)
Low noise overshoot and undershoot < 10 % of VCC
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G08GM-Q100 | 0.8?-?3.6 | CMOS | ± 1.9 | 8.2 | 70 | 1 | ultra low | -40~125 | 311 | 7.7 | 157 | XSON6 |
| 74AUP1G08GW-Q100 | 0.8?-?3.6 | CMOS | ± 1.9 | 8.2 | 70 | 1 | ultra low | -40~125 | 309 | 79.2 | 179 | TSSOP5 |
| 74AUP1G08GZ-Q100 | 0.8?-?3.6 | CMOS | ultra low | -40~125 | XSON5 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP1G08GM-Q100 | 74AUP1G08GM-Q100X (935690769115) |
Active | pE |
XSON6 (SOT886) |
SOT886 |
REFLOW_BG-BD-1
|
SOT886_115 |
| 74AUP1G08GW-Q100 | 74AUP1G08GW-Q100H (935300359125) |
Active | pE |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
| 74AUP1G08GZ-Q100 | 74AUP1G08GZ-Q100YL (935691684315) |
Active | pE |
XSON5 (SOT8065-1) |
SOT8065-1 | SOT8065-1_315 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP1G08GM-Q100 | 74AUP1G08GM-Q100X | 74AUP1G08GM-Q100 |
|
|
| 74AUP1G08GW-Q100 | 74AUP1G08GW-Q100H | 74AUP1G08GW-Q100 |
|
|
| 74AUP1G08GZ-Q100 | 74AUP1G08GZ-Q100YL | 74AUP1G08GZ-Q100 |
|
|
文檔 (20)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AUP1G08_Q100 | Low-power 2-input AND gate | Data sheet | 2024-09-20 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT886 | 3D model for products with SOT886 package | Design support | 2019-10-03 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| SOT8065-1 | 3D model for products with SOT8065-1 package | Design support | 2024-11-05 |
| aup1g08 | 74AUP1G08 IBIS model | IBIS model | 2014-12-14 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| Leaflet_SOT8065_Minilogic | Leaflet_SOT8065 Minilogic | Leaflet | 2024-11-15 |
| DFN1410-6_SOT886_mk | plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| XSON6_SOT886_mk | plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
| SOT886 | plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Package information | 2022-06-01 |
| SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
| SOT8065-1 | Plastic thermal enhanced extremely thin small outline package withside-wettable flanks (SWF); no leads; 5 terminals; body 1.1 × 0.85 × 0.5mm | Package information | 2024-08-28 |
| REFLOW_BG-BD-1 | Reflow soldering profile | Reflow soldering | 2021-04-06 |
| MAR_SOT886 | MAR_SOT886 Topmark | Top marking | 2013-06-03 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
支持
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模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| SOT886 | 3D model for products with SOT886 package | Design support | 2019-10-03 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| SOT8065-1 | 3D model for products with SOT8065-1 package | Design support | 2024-11-05 |
| aup1g08 | 74AUP1G08 IBIS model | IBIS model | 2014-12-14 |
Ordering, pricing & availability
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