74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
The 74LVC377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50 Ω transmission lines at 125 °C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC377D | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 6.0 | 230 | low | -40~125 | 85 | 27.7 | 61 | SO20 |
| 74LVC377PW | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 6.0 | 230 | low | -40~125 | 101 | 4.7 | 45 | TSSOP20 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC377D | 74LVC377D,118 (935210660118) |
Active | 74LVC377D |
SO20 (SOT163-1) |
SOT163-1 |
WAVE_BG-BD-1
|
SOT163-1_118 |
| 74LVC377PW | 74LVC377PW,118 (935210680118) |
Active | LVC377 |
TSSOP20 (SOT360-1) |
SOT360-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT360-1_118 |
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC377DB | 74LVC377DB,112 (935210670112) |
Obsolete | no package information | ||||
| 74LVC377DB,118 (935210670118) |
Obsolete | ||||||
環境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC377D | 74LVC377D,118 | 74LVC377D |
|
|
| 74LVC377PW | 74LVC377PW,118 | 74LVC377PW |
|
|
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC377DB | 74LVC377DB,112 | 74LVC377DB |
|
|
| 74LVC377DB | 74LVC377DB,118 | 74LVC377DB |
|
|
文檔 (14)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC377 | Octal D-type flip-flop with data enable; positive-edge trigger | Data sheet | 2023-08-28 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| SOT163-1 | 3D model for products with SOT163-1 package | Design support | 2020-01-22 |
| SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
| lvc377 | lvc377 IBIS model | IBIS model | 2013-04-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP20_SOT360-1_mk | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT163-1 | plastic, small outline package; 20 leads; 1.27 mm pitch; 12.8 mm x 7.5 mm x 2.65 mm body | Package information | 2024-11-15 |
| SOT360-1 | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.2 mm body | Package information | 2024-11-15 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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