74HC112-Q100; 74HCT112-Q100
Dual JK flip-flop with set and reset; negative-edge trigger
The 74HC112-Q100; 74HCT112-Q100 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Features and benefits
Input levels:
For 74HC112-Q100: CMOS level
For 74HCT112-Q100: TTL level
Asynchronous set and reset
Specified in compliance with JEDEC standard no. 7A
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC112PW-Q100 | 2.0?-?6.0 | CMOS | ± 5.2 | 17 | 66 | low | -40~125 | 109 | 1 | 36.7 | TSSOP16 |
| 74HCT112D-Q100 | 4.5?-?5.5 | TTL | ± 4 | 19 | 70 | low | -40~125 | 75 | 1.7 | 33 | SO16 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC112PW-Q100 | 74HC112PW-Q100J (935691580118) |
Active | HC112 |
TSSOP16 (SOT403-1) |
SOT403-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT403-1_118 |
| 74HCT112D-Q100 | 74HCT112D-Q100J (935691595118) |
Active | 74HCT112D |
SO16 (SOT109-1) |
SOT109-1 |
SO-SOJ-REFLOW
SO-SOJ-WAVE WAVE_BG-BD-1 |
SOT109-1_118 |
環境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HC112PW-Q100 | 74HC112PW-Q100J | 74HC112PW-Q100 |
|
|
| 74HCT112D-Q100 | 74HCT112D-Q100J | 74HCT112D-Q100 |
|
|
文檔 (13)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74HC_HCT112_Q100 | Dual JK flip-flop with set and reset; negative-edge trigger | Data sheet | 2024-01-15 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| SOT403-1 | 3D model for products with SOT403-1 package | Design support | 2020-01-22 |
| SOT109-1 | 3D model for products with SOT109-1 package | Design support | 2020-01-22 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP16_SOT403-1_mk | plastic, thin shrink small outline package; 16 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SO16_SOT109-1_mk | plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.35 mm body | Marcom graphics | 2017-01-28 |
| SOT403-1 | plastic, thin shrink small outline package; 16 leads; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-08 |
| SOT109-1 | plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.75 mm body | Package information | 2023-11-07 |
| SO-SOJ-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
| SO-SOJ-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
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